The demand for high illumination light emitting devices continues to increase, often requiring multiple light emitting elements to be packaged as a single light emitting device. Chip Scale Package light emitting devices (CSP-LEDs) are well suited for such applications because the wafer upon which individual devices are grown can be sliced to include any number of devices, arranged in arrays of different sizes and shapes.
FIG. 1A illustrates an example segment of a wafer 100 that includes a plurality of CSP-LEDs 110, each CSP-LED 110 having a pair of bond pads 120N and 120P for coupling to the n-type and p-type layers of the light emitting element that sandwich a light emitting layer (not illustrated).
FIG. 1B illustrates example slice configurations (dashed bold lines) 130 to produce pairs of CSP-LEDs a first pair containing CSP-LEDS 110A and 110B, and a second pair containing CSP-LEDs 110C and 110D, as well as many other pairs. FIG. 1C illustrates example slice configurations 140 to produce a 2×2 array of CSP-LEDs 110A-110D.
The particular connections of multiple CSP-LEDs to a power source determines the nominal operating voltage of the multiple CSP-LED die. If two CSP-LEDs are arranged in series, the nominal operating voltage of the die is twice the nominal operating voltage of a single CSP-LED; if they are arranged in parallel, the nominal operating voltage of the die is equal to the nominal operating voltage of a single CSP-LED.
If it is known a priori how the multiple CSP-LEDs are to be coupled together, one or more interconnection layers (not illustrated) may be added at the wafer level to enable external coupling to only two contacts on the sliced segment. For example, if the multiple CSP-LEDs are to be configured in parallel, the interconnect layer(s) may couple all of the n-type regions together to form a single N-contact, and all of the p-type regions together to form a single P-contact. In like manner, if the multiple CSP-LEDs are to be coupled in series, the interconnect layer(s) may couple all but one of the n-type regions to a p-type region of an adjacent CSP-LED, the uncoupled n-type region forming the N-contact to the series arrangement, and the remaining uncoupled p-type region forming the P-contact to the series arrangement.
Alternatively, if it is not known how the multiple CSP-LEDs may be coupled, the wafer is sliced with each bond pad isolated from each other bond pad, and the desired interconnection among the CSP-LEDs is provided on the substrate to which the sliced die is mounted. Often, however, achieving the desired interconnection may require the use of a substrate with multiple interconnect layers.
FIG. 2A illustrates a need to use multiple interconnect layers to couple the example 2×2 array of CSP-LEDs in series. For convenience, the pairs of bond pads are labeled N1-P1, N2-P2, N3-P3, and N4-P4. The illustrated conductive segments 211-213 and 260, 270 would be on a substrate (not illustrated), and would provide the illustrated interconnections when the die is mounted on the substrate. The conductive segments 211, 212, and 213 couple P1 to N2, P2 to N3, and P3 to N4, respectively. Pads N1 is the N-contact to the series arrangement, and P4 is the P-contact.
To operate this series arrangement, an external source 250 must be coupled to the N1 and P4 pads using example interconnects 260, 270. Typically, conductive 270 connects pad P4 to the positive side external source 250. However, as can be seen, access to pad P4 is blocked by conductive segment 212, and will require a conductive segment 240 that crosses over the segment 212 without contact. ‘Through holes’ to the underside of the substrate, or ‘vias’ to internal layers of the substrate, are typically required to provide the required connection of the P4 pad to conductive segment 270 on another layer. In the alternative the interconnection 212 may be moved to this other layer.
Had it been known a priori that the multiple CSP-LEDs were intended to be arranged in series, the orientation of the bond pads N3-P3 and N4-P4 could have been reversed on the wafer, as illustrated in FIG. 2B. In this example, pads N1 and P3 form the N and P contacts, which can be coupled via conductive segments 260, 270 to an external source 250 using the same layer as the conductive segments 221, 222, and 223. However, with the arrangement of bond pads in FIG. 2B, coupling the multiple CSP-LEDs in parallel will require the use of multiple conductive layers on the substrate.
The customization of the arrangement of pads on a die to satisfy the requirements of particular applications, such as illustrated in FIG. 2B, however, requires individual design and fabrication for each of these applications. If the quantity of dies needed for an application does not warrant such a customization, a multi-layer substrate may be required. Even if the application's quantity of dies warrants such a customization, a more efficient economy of scale could be achieved if the different applications could all use a common die pad arrangement.